Workshops, Tutorials & Events

Program

***  Important notice ***

****  Registration to ALL tutorials and workshops is still OPEN!!!! **** 

Tutorial/Workshop with less than minimum number of pre-registrations will be canceled and people who paid for it could change their selection or get their money back.

 

 Workshops (D – Day, H – Half)

E1 EU-FP7 Synopsis of FP7 Computer Systems and Transitioning to Horizon 2020 H
E2 Roadmap Challenges and Roadmaps in Computer Architectures – the Next Decade D
W1 ESSA Third Workshop on Energy-Secure System Architectures D
W2 WIVOSCA The 7th Annual Workshop on the Interaction between Operating System and Computer Architecture D
W3 DaSi The Dark Sllicon Workshop – workshop was cancelled. D
W4 WDDD Workshop on Duplicating, Deconstructing, and Debunking — workshop was cancelled. H
W5 ETNA The 1st International Workshop on Emerging Topics in NoC-aware Computer Architecture H
W6 WEED

Fifth Workshop on Energy-Efficient Design

H
W7 HASP Hardware and Architectural Support for Security and Privacy D
W8 ASBD Third Workshop on Architectures and Systems for Big Data H
W9 BIC Brain Inspired Computing D
W10 MES Many-Core Embedded Systems D
W11 AMAS-BT 5th Workshop on Architectural and Microarchitectural Support for Binary Translation H

 


 Tutorials (D – Day, H – Half)

T1 PMU Tutorial on PMU-based Analysis Methodologies and Tools D
T2 Xeon Phi Intel Xeon Phi, HW architecture and programming model D
T3 CloudSuite2 CloudSuite2 on Flexus D
T5 RDMA Remote Direct Memory Access (RDMA) for Eliminating Data Center Application Performance Bottlenecks H
T6 OMPSs Hybrid and Heterogeneous Parallel Programming with MPI/OmpSs for Exascale Systems D
T7 Multi2Sim Multi-Architecture CPU, GPU, and APU Simulation with Multi2Sim H
T8 GPGPUsim GPUWattch+GPGPU-Sim: A Framework for Energy-Aware Optimizations in Manycore Architectures H
T9 Pin! Detailed Pin! Binary Instrumentation Engine H
T10
COST-ET
(formerly named EETCO)
An Estimation and Design Space Exploration Tool for Datacenters TCO H
T11 HASim HAsim FPGA-Based Processor Models:  Fast, Accurate and Flexible H
T12 Maxeler Control-Flow versus Data-Flow Supercomputers, and the Maxeler Programming Paradigm H